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data sheet ics851010ayi revision a august 2, 2010 1 ?2010 integrated device technology, inc. 1-to-10, differential hcsl fanout buffer ICS851010I general description the ICS851010I is a 1-to-10 differential hcsl fanout buffer. the ICS851010I is designed to translate any differential signal levels to differential hcsl output levels. an external reference resistor is used to set the value of the current supplied to an external load. the load resistor value is chosen to equal the value of the characteristic line impedance of 50 ? . the ICS851010I is characterized at an operating supply voltage of 3.3v. the differential hcsl outputs, accurate crossover voltage and symmetric duty cycle makes the ICS851010I ideal for interfacing to pci express and fbdimm applications. features ? ten differential hcsl outputs ? translates any differential input signal (lvpecl, lvhstl, lvds, hcsl) to hcsl levels without external bias networks ? maximum output frequency: 250mhz ? output skew: 165ps (maximum) ? output drift: 140ps (maximum) ? v oh : 850mv (maximum) ? additive phase jitter, rms: 0.19ps (typical) ? full 3.3v supply voltage ? available in lead-free (rohs 6) package ? -40c to 85c ambient operating temperature q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q9 nq9 q8 nq8 q7 nq7 q6 nq6 q5 nq5 clk nclk iref 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 q0 nq0 v dd q1 nq1 q2 nq2 v dd nq7 q7 v dd nq6 q6 nq5 q5 v dd gnd iref q3 nq3 v dd v dd q4 nq4 q9 v dd nq8 q8 ncl k clk gnd nq9 pin assignment block diagram ICS851010I 32-lead tqfp, e-pad 7mm x 7mm x1mm package body y package top view
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer ics851010ayi revision a august 2, 2010 2 ?2010 integrated device technology, inc. table 1. pin descriptions output driver current the ICS851010I outputs are hcsl differential current drive with the current being set with a resistor from i ref to ground. for a single load and a 50 ? pc board trace, the drive current would typically be set with a r ref of 950 ? which products an i ref of 1.16ma. the i ref is multiplied by a current mirror to an output drive of 12*1.16ma or 13.90ma. see figure 1 for current mirror and output drive details. r ref 950? r l r l i ref figure 1. hcsl current mirror and output drive number name type description 1, 2 q0, nq0 output differential output pair. differ ential hcsl interface levels. 3, 8, 13, 14, 17, 22, 30 v dd power positive supply pins. 4, 5 q1, nq1 output differential output pair. differ ential hcsl interface levels. 6, 7 q2, nq2 output differential output pair. differ ential hcsl interface levels. 9, 25 gnd power power supply ground. 10 iref input reference current input. used to se t the output current. connect to 950 ? resistor to ground. 11, 12 q3, nq3 output differential output pair. differ ential hcsl interface levels. 15, 16 q4, nq4 output differential output pair. differ ential hcsl interface levels. 18, 19 q5, nq5 output differential output pair. differ ential hcsl interface levels. 20, 21 q6, nq6 output differential output pair. differ ential hcsl interface levels. 23, 24 q7, nq7 output differential output pair. differ ential hcsl interface levels. 26 clk input non-inverting differential input. 27 nclk input inverting differential clock input. 28, 29 q8, nq8 output differential output pair. differ ential hcsl interface levels. 31, 32 q98, nq9 output differential output pair. differ ential hcsl interface levels.
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer ics851010ayi revision a august 2, 2010 3 ?2010 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functio nal operation of product at t hese conditions or any conditions beyond those listed in the dc cha racteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o -0.5v to v dd + 0.5v package thermal impedance, ja 32.2c/w (0 mps) storage temperature, t stg -65 c to 150 c dc electrical characteristics table 2a. power supply dc characteristics, v dd = 3.3v5%, t a = -40c to 85c note 1: measured using 200mhz input frequency. table 2b. differential dc characteristics, v dd = 3.3v5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . item rating symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v i dd power supply current; note 1 105 ma symbol parameter test conditio ns minimum typical maximum units i ih input high current clk, nclk v dd = v in = 3.465v 5 a i il input low current clk, nclk v dd = 3.465v, v in = 0v 5 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd ? 0.85 v
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer ics851010ayi revision a august 2, 2010 4 ?2010 integrated device technology, inc. ac electrical characteristics table 3. hcsl ac characteristics, v dd = 3.3v5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the dev ice is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: current adjust set for v oh = 0.7v. measurements refer to pciex outputs only. note: characterized using an r ref value of 950 ? resistor. note 1: measured from the differential input cross poin t to the differential output crossing point. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the differential output cross point. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross po int. note 5: output drift is measured as the change in the time placement of the differential cross point for each output on a given device due to a change in temperature and supply voltage. measured at the differential cross point. note 6: measurement using r ref = to 950 ? , r load = to 50 ? . note 7: measurement taken from single-ended waveform. note 8: measured at crossing point where the in stantaneous voltage value of the rising edg e of qx equals the falling edge of nqx. see parameter measurement information section. note 9: refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to a ll crossing points for this measurement. see para meter measurement information section. note 10: defined as the total variation of all crossing voltage of risi ng qx and falling nqx. this is the maximum allowed variance in t he v cross for any particular system. see parame ter measurement information section. note 11: measurement taken from differential waveform. note 12: measurement from -150mv to +150mv on the differential wavefo rm (derived from qx minus nqx) . the signal must be monotonic through the measurement region for rise and fall time. the 300mv measurement window is centered on the differential zero crossi ng. note 13: assuming 50% input duty cycle. data taken at ? 200mhz, unless otherwise specified. symbol parameter test conditi ons minimum typical maximum units f max output frequency 250 mhz t pd propagation delay, note 1 measured on at v ox 1.5 2.75 ns t sk(o) output skew; note 2, 3 measured on at v ox 165 ps t sk(pp) part-to-part skew; note 3, 4 800 ps t jit buffer additive phase jitter, rms clk = 155.52mhz, integration range: 12khz ? 20mhz 0.19 ps t sk(drift) output drift; note 5 140 ps v max absolute max output voltage; note 6 ? 150mhz 500 850 mv v min absolute min output voltage; note 6 ? 150mhz -150 150 mv v cross absolute crossing voltage; note 7, 8, 9 250 550 mv ? v cross total variation of v cross over all edges; note 7, 8, 10 140 mv t r / t f rise/fall edge rate; note 11, 12 0.6 4.0 v/ns odc output duty cycle; note 13 47 53 %
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer ics851010ayi revision a august 2, 2010 5 ?2010 integrated device technology, inc. parameter measureme nt information hcsl output load ac test circuit differential input levels part-to-part skew hcsl output load ac test circuit output skew propagation delay measurement point 33 ? 50 ? 50 ? 33 ? measurement point 49.9 ? 49.9 ? hcsl gnd 2pf 2pf v dd v dd v cmr cross points v pp v dd gnd nclk clk nqx qx nqy qy t sk(pp) part 1 part 2 950 ? 50 ? 50 ? hcsl gnd 0v scope iref this load condition is used for i dd, tsk(pp), tjit(?), t pd and tsk(o) measurements. 3.3v5% v dd nqx qx nqy qy t sk(o) t pd nclk clk nq[0:9] q[0:9]
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer ics851010ayi revision a august 2, 2010 6 ?2010 integrated device technology, inc. parameter measurement in formation, continued differential measurement points for duty cycle/period single-ended measurement points for delta cross point single-ended measurement points for absolute cross point and swing differential measurement points for rise/fall edge rate clock period (differential) positive duty cycle (differential) negative duty cycle (differential) q - nq 0.0v q nq ? v cross nq q v cross_max v cross_min v max v min q - nq -150mv +150mv 0.0v fall edge rate rise edge rate
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer ics851010ayi revision a august 2, 2010 7 ?2010 integrated device technology, inc. applications information recommendations for un used output pins o utputs: differential outputs all unused differential outputs ca n be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. wiring the differential input to accept single-ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requ ires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 2. recommended schematic for wiring a diff erential input to accept single-ended levels
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer ics851010ayi revision a august 2, 2010 8 ?2010 integrated device technology, inc. differential clock input interface the clk/nclk accepts hcsl, lv ds, lvpecl and sstl and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver co mponent to confirm the driver termination requirements. for example in figure 3a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. clk/nclk input driven by an idt open emitter lvhstl driver figure 3c. clk/nclk input driven by a 3.3v lvpecl driver figure 3e. clk/nclk input driven by a 3.3v hcsl driver figure 3b. clk/nclk input driven by a 3.3v lvpecl driver figure 3d. clk/nclk input driven by a 3.3v lvds driver figure 3f. clk/nclk input driven by an sstl driver r1 50 ? r2 50 ? 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v lvhstl idt lvhstl driver differential input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl differential input hcsl *r3 33 ? *r4 33 ? clk nclk 3.3v 3.3v zo = 50 ? zo = 50 ? differential input r1 50 ? r2 50 ? *optional ? r3 and r4 can be 0 ? clk nclk differential input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 ? r2 50 ? r2 50 ? 3.3v r1 100 lvds clk nclk 3.3v differential input zo = 50 ? zo = 50 ? sstl 2.5v zo = 60 ? zo = 60 ? 2.5v r1 120 r2 120 r3 120 r4 120 clk nclk 3.3v differential input
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer ics851010ayi revision a august 2, 2010 9 ?2010 integrated device technology, inc. epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadframe base package, amkor technology. figure 4. assembly for exposed pad thermal rel ease path - side view (drawing not to scale) ground plane land pattern solder thermal via exposed heat slug (ground pad) pin pin pad solder pin pin pad solder
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer ics851010ayi revision a august 2, 2010 10 ?2010 integrated device technology, inc. recommended termination figure 5a is the recommended termination for applications which require the receiver and driver to be on a separate pcb. all traces should be 50 ? impedance. figure 5a. recommended termination figure 5b is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same pcb. all traces should all be 50 ? impedance. figure 5b. recommended termination
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer ics851010ayi revision a august 2, 2010 11 ?2010 integrated device technology, inc. power considerations this section provides information on power dissipa tion and junction temperature for the ICS851010I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS851010I is the sum of the core power plus the power dissipated in the load(s). the follo wing is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. power (core) max = v dd_max * i dd_max = 3.465v * 105ma = 363.825mw power (outputs) max = 44.5mw/loaded output pair if all outputs are loaded, the total power is 10 * 44.5mw = 445mw total power_ max (3.465v, with all outputs s witching) = 363.825mw + 445mw = 808.825mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 32.2c/w per table 4 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.809w * 32.2c/w = 111c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 4. thermal resistance ja for 32 lead tqfp, e-pad, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 32.2c/w 26.3c/w 24.7c/w
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer ics851010ayi revision a august 2, 2010 12 ?2010 integrated device technology, inc. the purpose of this section is to calculate power dissipation on the ic per hcsl output pair. hcsl output driver circuit and termination are shown in figure 6. v dd v out r l 50 ? ic ? i out = 17ma r ref = 950 ? 1% figure 6. hcsl driver circuit and termination hcsl is a current steering output which sources a maximum of 17ma of current per output. to calculate worst case on-chip power dissipation, use the following equations which assume a 50 ? load to ground. the highest power dissipation occurs when v dd _ max . power = (v dd_max ? v out ) * i out , since v out ? i out * r l = (v dd_max ? i out * r l ) * i out = (3.465v ? 17ma * 50 ? ) * 17ma total power dissipation per output pair = 44 .5mw
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer ics851010ayi revision a august 2, 2010 13 ?2010 integrated device technology, inc. reliability information table 5. ja vs. air flow table for a 32 lead tqfp, e-pad transistor count the transistor count for ICS851010I is: 843 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 32.2c/w 26.3c/w 24.7c/w
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer ics851010ayi revision a august 2, 2010 14 ?2010 integrated device technology, inc. package outline and package dimensions package outline - y suffix for 32 lead tqfp, e-pad table 6. package dimensions 32 lead tqfp, e-pad reference document: jedec publication 95, ms-026 -hd version exposed pad down -tab, exposed part of connection bar or tie bar 0.20 tab jedec variation: abc - hd all dimensions in millimeters symbol minimum nominal maximum n 32 a 1.20 a1 0.05 0.10 0.15 a2 0.95 1.00 1.05 b 0.30 0.35 0.40 c 0.09 0.20 d & e 9.00 basic d1 & e1 7.00 basic d2 & e2 5.60 ref. d3 & e3 3.0 4.0 e 0.80 basic l 0.45 0.60 0.75 0 7 ccc 0.10
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer ics851010ayi revision a august 2, 2010 15 ?2010 integrated device technology, inc. ordering information table 7. ordering information note: parts that are ordered with an ?lf? suffix to the part number are the pb-free configuration and are rohs compliant part/order number marking package shipping packaging temperature 851010ayilf ics851010ail lead-free, 32 lead tqfp, e-pad tray -40 c to 85 c 851010ayilft ics851010ail lead-free, 32 lead tqfp, e-pad 1000 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requirin g high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer ics851010ayi revision a august 2, 2010 16 ?2010 integrated device technology, inc. revision history sheet rev table page description of change date a 2 7 14 corrected output driver current. updated wiring the differential input to accept single-ended levels. updated package outline. converted datasheet format. 7/21/10 a 5 parameter measurement information - corrected label names on output skew and part-to-part skew. 8/2/10
ICS851010I data sheet 1-to-10 differential hcsl fanout buffer disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features a nd performance, is subject to change wit hout notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informati on contained herein is provided without re presentation or warranty of any kind, whether express or implied, in cluding, but not limited to, the suitability of idt?s products for any particular purpose, an im plied warranty of merchantabilit y, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property right s of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ris k, absent an express, written agreement by idt. integrated device technology, idt and the idt l ogo are registered trademarks of idt. ot her trademarks and service marks used he rein, including protected names, logos and designs, ar e the property of idt or their respective third party owners. copyright 2010. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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